1. Field of the Invention
The present invention relates to fabricating a memory device. In particular, the present invention provides a method for fabricating a semiconductor device, and more specifically to a method for fabricating a semiconductor device wherein during an etching process for forming a recess gate region, a device isolation film is etched using a mask partially exposing a channel region and its neighboring device isolation film, and then a semiconductor substrate is etched to prevent a silicon horn in the recess gate region from being formed, thus increasing a margin for the etching process.
2. Discussion of the Related Art
FIG. 1 is a simplified layout of one semiconductor device.
Referring to FIG. 1, a device isolation film 40, an active region 10a and a gate structure 120 as a word line passing across the active region 10a are formed on a semiconductor substrate. A distance between the neighboring gate structures 120 is F, which is the minimum line width according to the design rules. A line-type recess gate region 60 is disposed under the gate structure 120. The line width of the recess gate region 60 is 2D smaller than that of the gate structure 120. That is, a misalignment margin of the recess gate region 60 is D.
FIGS. 2A through 2F are simplified cross-sectional views illustrating a conventional method for fabricating a semiconductor device, wherein FIGS. 2A(i) through 2F(i) are cross-sectional views taken along the line I-I′ of FIG. 1 and FIGS. 2A(ii) through 2F(ii) are cross-sectional views taken along the line II-II′ of FIG. 1.
Referring to FIG. 2A, a pad oxide film 20 and a pad nitride film 30 are deposited on a semiconductor substrate 10. Next, a device isolation film 40 defining an active region 10a is formed by performing an STI process.
Referring to FIG. 2B, the device isolation film 40 is etched to lower the height of the device isolation film 40. The pad nitride film 30 is then removed. Next, a polysilicon layer 50 is formed on the entire surface.
Referring to FIG. 2C, a photoresist film (not shown) is formed on the polysilicon layer 50, and then exposed and developed using an exposure mask defining the recess gate region 60 of FIG. 1 to form a line-type mask pattern (not shown) exposing the recess gate region 60. Next, the exposed polysilicon layer 50 and the pad oxide film 20 are etched using the mask pattern as an etching mask to form a polysilicon layer pattern 50a and a pad oxide film pattern 20a defining the recess gate region 60. Thereafter, the mask pattern is removed.
Referring to FIG. 2D, the exposed semiconductor substrate 10 is etched using the polysilicon layer pattern 50a as an etching mask to form a recess gate region 70. Here, the etching process may be performed to simultaneously etch the semiconductor substrate 10 and the polysilicon layer pattern 50a. At this time, the etching rate of the semiconductor substrate 10 closest to the device isolation film 40 is slower than that of the semiconductor substrate 10 spaced apart from the device isolation film 40, thereby forming a silicon horn ‘A’ on the semiconductor substrate 10 within the recess gate region 70. Next, the pad oxide film pattern 20a is removed.
Referring to FIG. 2E, a gate oxide film 80 is formed on the surface of the exposed semiconductor substrate 10. Thereafter, a lower gate electrode layer 90 filling up the recess gate region 70 is formed on the entire surface. An upper gate electrode layer 100 and a hard mask layer 110 are then sequentially deposited on the lower gate electrode layer 90.
Referring to FIG. 2F, the hard mask layer 110, the upper gate electrode layer 100 and the lower gate electrode layer 90 are patterned to form a gate structure 120 consisting of a stacked structure 120 of a lower gate electrode 90a, an upper gate electrode 100a and a hard mask layer pattern 110a. 
FIG. 3 is a cross-sectional view illustrating misalignment occurring during the process of forming the recess gate region according to the conventional method for fabricating a semiconductor device.
Referring to FIG. 3, in case of misalignment occurring between a recess gate mask and a device isolation film mask by M larger than D such a maximum misalignment, the semiconductor substrate 10 of M-D between the device isolation film 40 and the polysilicon layer pattern 50a is exposed.
Accordingly, the exposed semiconductor substrate 10 as unwanted portion is abnormally etched during the etching process of FIG. 2D. As the size of the semiconductor device is reduced, the process margin for manufacturing the semiconductor device is also reduced. If the misalignment is increased, a problem occurs in which the unwanted semiconductor substrate shown in FIG. 3 is exposed and then abnormally etched. In addition, the silicon horn within the recess gate region is formed to lower the threshold voltage for a cell transistor and increase its leakage current, thus degrading the refresh characteristic of the device.